$OpenBSD: patch-gcc_config_sh_sh_h,v 1.1 2013/02/04 21:23:40 tobiasu Exp $
--- gcc/config/sh/sh.h.orig	Tue Jan 29 02:01:36 2013
+++ gcc/config/sh/sh.h	Tue Jan 29 02:04:51 2013
@@ -233,9 +233,6 @@ do { \
 #define TARGET_DIVIDE_INV20L (sh_div_strategy == SH_DIV_INV20L)
 #define TARGET_DIVIDE_INV_CALL (sh_div_strategy == SH_DIV_INV_CALL)
 #define TARGET_DIVIDE_INV_CALL2 (sh_div_strategy == SH_DIV_INV_CALL2)
-#define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1)
-#define TARGET_DIVIDE_CALL_FP (sh_div_strategy == SH_DIV_CALL_FP)
-#define TARGET_DIVIDE_CALL_TABLE (sh_div_strategy == SH_DIV_CALL_TABLE)
 
 #define SELECT_SH1               (MASK_SH1)
 #define SELECT_SH2               (MASK_SH2 | SELECT_SH1)
@@ -494,24 +491,16 @@ do {									\
 extern int assembler_dialect;
 
 enum sh_divide_strategy_e {
-  /* SH5 strategies.  */
   SH_DIV_CALL,
   SH_DIV_CALL2,
-  SH_DIV_FP, /* We could do this also for SH4.  */
+  SH_DIV_FP,
   SH_DIV_INV,
   SH_DIV_INV_MINLAT,
   SH_DIV_INV20U,
   SH_DIV_INV20L,
   SH_DIV_INV_CALL,
   SH_DIV_INV_CALL2,
-  SH_DIV_INV_FP,
-  /* SH1 .. SH4 strategies.  Because of the small number of registers
-     available, the compiler uses knowledge of the actual set of registers
-     being clobbered by the different functions called.  */
-  SH_DIV_CALL_DIV1, /* No FPU, medium size, highest latency.  */
-  SH_DIV_CALL_FP,     /* FPU needed, small size, high latency.  */
-  SH_DIV_CALL_TABLE,  /* No FPU, large size, medium latency. */
-  SH_DIV_INTRINSIC
+  SH_DIV_INV_FP
 };
 
 extern enum sh_divide_strategy_e sh_div_strategy;
@@ -520,231 +509,7 @@ extern enum sh_divide_strategy_e sh_div_strategy;
 #define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL
 #endif
 
-#define OVERRIDE_OPTIONS 						\
-do {									\
-  int regno;								\
-									\
-  if (flag_finite_math_only == 2)					\
-    flag_finite_math_only						\
-      = !flag_signaling_nans && TARGET_SH2E && ! TARGET_IEEE;		\
-  if (TARGET_SH2E && !flag_finite_math_only)				\
-    target_flags |= MASK_IEEE;						\
-  sh_cpu = CPU_SH1;							\
-  assembler_dialect = 0;						\
-  if (TARGET_SH2)							\
-    sh_cpu = CPU_SH2;							\
-  if (TARGET_SH2E)							\
-    sh_cpu = CPU_SH2E;							\
-  if (TARGET_SH2A)							\
-    {									\
-      sh_cpu = CPU_SH2A;						\
-      if (TARGET_SH2A_DOUBLE)						\
-        target_flags |= MASK_FMOVD;					\
-    }									\
-  if (TARGET_SH3)							\
-    sh_cpu = CPU_SH3;							\
-  if (TARGET_SH3E)							\
-    sh_cpu = CPU_SH3E;							\
-  if (TARGET_SH4)							\
-    {									\
-      assembler_dialect = 1;						\
-      sh_cpu = CPU_SH4;							\
-    }									\
-  if (TARGET_SH4A_ARCH)							\
-    {									\
-      assembler_dialect = 1;						\
-      sh_cpu = CPU_SH4A;						\
-    }									\
-  if (TARGET_SH5)							\
-    {									\
-      sh_cpu = CPU_SH5;							\
-      target_flags |= MASK_ALIGN_DOUBLE;				\
-      if (TARGET_SHMEDIA_FPU)						\
-	target_flags |= MASK_FMOVD;					\
-      if (TARGET_SHMEDIA)						\
-	{								\
-	  /* There are no delay slots on SHmedia.  */			\
-	  flag_delayed_branch = 0;					\
-	  /* Relaxation isn't yet supported for SHmedia */		\
-	  target_flags &= ~MASK_RELAX;					\
-	  /* After reload, if conversion does little good but can cause \
-	     ICEs:							\
-	     - find_if_block doesn't do anything for SH because we don't\
-	       have conditional execution patterns.  (We use conditional\
-	       move patterns, which are handled differently, and only	\
-	       before reload).						\
-	     - find_cond_trap doesn't do anything for the SH because we \	
-	       don't have conditional traps.				\
-	     - find_if_case_1 uses redirect_edge_and_branch_force in	\
-	       the only path that does an optimization, and this causes	\
-	       an ICE when branch targets are in registers.		\
-	     - find_if_case_2 doesn't do anything for the SHmedia after	\
-	       reload except when it can redirect a tablejump - and	\
-	       that's rather rare.  */					\
-	  flag_if_conversion2 = 0;					\
-	  if (! strcmp (sh_div_str, "call"))				\
-	    sh_div_strategy = SH_DIV_CALL;				\
-	  else if (! strcmp (sh_div_str, "call2"))			\
-	    sh_div_strategy = SH_DIV_CALL2;				\
-	  if (! strcmp (sh_div_str, "fp") && TARGET_FPU_ANY)		\
-	    sh_div_strategy = SH_DIV_FP;				\
-	  else if (! strcmp (sh_div_str, "inv"))			\
-	    sh_div_strategy = SH_DIV_INV;				\
-	  else if (! strcmp (sh_div_str, "inv:minlat"))			\
-	    sh_div_strategy = SH_DIV_INV_MINLAT;			\
-	  else if (! strcmp (sh_div_str, "inv20u"))			\
-	    sh_div_strategy = SH_DIV_INV20U;				\
-	  else if (! strcmp (sh_div_str, "inv20l"))			\
-	    sh_div_strategy = SH_DIV_INV20L;				\
-	  else if (! strcmp (sh_div_str, "inv:call2"))			\
-	    sh_div_strategy = SH_DIV_INV_CALL2;				\
-	  else if (! strcmp (sh_div_str, "inv:call"))			\
-	    sh_div_strategy = SH_DIV_INV_CALL;				\
-	  else if (! strcmp (sh_div_str, "inv:fp"))			\
-	    {								\
-	      if (TARGET_FPU_ANY)					\
-		sh_div_strategy = SH_DIV_INV_FP;			\
-	      else							\
-		sh_div_strategy = SH_DIV_INV;				\
-	    }								\
-	}								\
-      /* -fprofile-arcs needs a working libgcov .  In unified tree	\
-	 configurations with newlib, this requires to configure with	\
-	 --with-newlib --with-headers.  But there is no way to check	\
-	 here we have a working libgcov, so just assume that we have.  */\
-      if (profile_flag)							\
-	warning (0, "profiling is still experimental for this target");\
-    }									\
-  else									\
-    {									\
-       /* Only the sh64-elf assembler fully supports .quad properly.  */\
-       targetm.asm_out.aligned_op.di = NULL;				\
-       targetm.asm_out.unaligned_op.di = NULL;				\
-    }									\
-  if (TARGET_SH1)							\
-    {									\
-      if (! strcmp (sh_div_str, "call-div1"))				\
-	sh_div_strategy = SH_DIV_CALL_DIV1;				\
-      else if (! strcmp (sh_div_str, "call-fp")				\
-	       && (TARGET_FPU_DOUBLE					\
-		   || (TARGET_HARD_SH4 && TARGET_SH2E)			\
-		   || (TARGET_SHCOMPACT && TARGET_FPU_ANY)))		\
-	sh_div_strategy = SH_DIV_CALL_FP;				\
-      else if (! strcmp (sh_div_str, "call-table") && TARGET_SH2)	\
-	sh_div_strategy = SH_DIV_CALL_TABLE;				\
-      else								\
-	/* Pick one that makes most sense for the target in general.	\
-	   It is not much good to use different functions depending	\
-	   on -Os, since then we'll end up with two different functions	\
-	   when some of the code is compiled for size, and some for	\
-	   speed.  */							\
-									\
-	/* SH4 tends to emphasize speed.  */				\
-	if (TARGET_HARD_SH4)						\
-	  sh_div_strategy = SH_DIV_CALL_TABLE;				\
-	/* These have their own way of doing things.  */		\
-	else if (TARGET_SH2A)						\
-	  sh_div_strategy = SH_DIV_INTRINSIC;				\
-	/* ??? Should we use the integer SHmedia function instead?  */	\
-	else if (TARGET_SHCOMPACT && TARGET_FPU_ANY)			\
-	  sh_div_strategy = SH_DIV_CALL_FP;				\
-        /* SH1 .. SH3 cores often go into small-footprint systems, so	\
-	   default to the smallest implementation available.  */	\
-	else if (TARGET_SH2)	/* ??? EXPERIMENTAL */			\
-	  sh_div_strategy = SH_DIV_CALL_TABLE;				\
-	else								\
-	  sh_div_strategy = SH_DIV_CALL_DIV1;				\
-    }									\
-  if (!TARGET_SH1)							\
-    TARGET_PRETEND_CMOVE = 0;						\
-  if (sh_divsi3_libfunc[0])						\
-    ; /* User supplied - leave it alone.  */				\
-  else if (TARGET_DIVIDE_CALL_FP)					\
-    sh_divsi3_libfunc = "__sdivsi3_i4";					\
-  else if (TARGET_DIVIDE_CALL_TABLE)					\
-    sh_divsi3_libfunc = "__sdivsi3_i4i";				\
-  else if (TARGET_SH5)							\
-    sh_divsi3_libfunc = "__sdivsi3_1";					\
-  else									\
-    sh_divsi3_libfunc = "__sdivsi3";					\
-  if (TARGET_FMOVD)							\
-    reg_class_from_letter['e' - 'a'] = NO_REGS;				\
-									\
-  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)		\
-    if (! VALID_REGISTER_P (regno))					\
-      sh_register_names[regno][0] = '\0';				\
-									\
-  for (regno = 0; regno < ADDREGNAMES_SIZE; regno++)			\
-    if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno)))			\
-      sh_additional_register_names[regno][0] = '\0';			\
-									\
-  if (flag_omit_frame_pointer < 0)					\
-   {									\
-     /* The debugging information is sufficient,			\
-        but gdb doesn't implement this yet */				\
-     if (0)								\
-      flag_omit_frame_pointer						\
-        = (PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG);			\
-     else								\
-      flag_omit_frame_pointer = 0;					\
-   }									\
-									\
-  if ((flag_pic && ! TARGET_PREFERGOT)					\
-      || (TARGET_SHMEDIA && !TARGET_PT_FIXED))				\
-    flag_no_function_cse = 1;						\
-									\
-  if (SMALL_REGISTER_CLASSES)						\
-    {									\
-      /* Never run scheduling before reload, since that can		\
-	 break global alloc, and generates slower code anyway due	\
-	 to the pressure on R0.  */					\
-      /* Enable sched1 for SH4; ready queue will be reordered by	\
-	 the target hooks when pressure is high. We can not do this for \
-	 SH3 and lower as they give spill failures for R0.  */		\
-      if (!TARGET_HARD_SH4) 						\
-        flag_schedule_insns = 0;		 			\
-      /* ??? Current exception handling places basic block boundaries	\
-	 after call_insns.  It causes the high pressure on R0 and gives	\
-	 spill failures for R0 in reload.  See PR 22553 and the thread	\
-	 on gcc-patches							\
-         <http://gcc.gnu.org/ml/gcc-patches/2005-10/msg00816.html>.  */	\
-      else if (flag_exceptions)						\
-	{								\
-	  if (flag_schedule_insns == 1)		 			\
-	    warning (0, "ignoring -fschedule-insns because of exception handling bug");	\
-	  flag_schedule_insns = 0;		 			\
-	}								\
-    }									\
-									\
-  if (align_loops == 0)							\
-    align_loops =  1 << (TARGET_SH5 ? 3 : 2);				\
-  if (align_jumps == 0)							\
-    align_jumps = 1 << CACHE_LOG;					\
-  else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2))			\
-    align_jumps = TARGET_SHMEDIA ? 4 : 2;				\
-									\
-  /* Allocation boundary (in *bytes*) for the code of a function.	\
-     SH1: 32 bit alignment is faster, because instructions are always	\
-     fetched as a pair from a longword boundary.			\
-     SH2 .. SH5 : align to cache line start.  */			\
-  if (align_functions == 0)						\
-    align_functions							\
-      = TARGET_SMALLCODE ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG);	\
-  /* The linker relaxation code breaks when a function contains		\
-     alignments that are larger than that at the start of a		\
-     compilation unit.  */						\
-  if (TARGET_RELAX)							\
-    {									\
-      int min_align							\
-	= align_loops > align_jumps ? align_loops : align_jumps;	\
-									\
-      /* Also take possible .long constants / mova tables int account.	*/\
-      if (min_align < 4)						\
-	min_align = 4;							\
-      if (align_functions < min_align)					\
-	align_functions = min_align;					\
-    }									\
-} while (0)
+#define OVERRIDE_OPTIONS sh_override_options ()
 
 /* Target machine storage layout.  */
 
